1. Field of the Invention
The present invention relates to information handling systems, and more particularly to multibit high speed multipliers for use in large processors in information handling systems.
2. Description of the Prior Art
The following are systems representative of the prior art.
Weinberger, U.S. Pat. No. 4,463,439, shows a carry save adder of a type which could be used to implement the 5-2 adder and 4-2 adder which form component parts of a preferred embodiment of the present invention.
The patent does not teach a high speed multiplier in accordance with the present invention.
Letteney, et. al., U.S. Pat. No. 4,228,520, is a prior art high speed multiply apparatus which has a first stage of 4-2 carry save adders which then feed four bit parallel adders each having four sum outputs and a carry output frm the highest order bit position. The 4 bit parallel adders function as a 2-1 adder.
A preferred embodiment of the present invention employs 5-2 carry save adder for the first stage with a next stage consisting of a 4-2 carry save adder and then a spill adder for a first part of a result and a full adder for a second part of a result wherein the logic is run at a double frequency clocking rate to achieve a performance of 20 bits per cycle as compared to 8 bits per cycle for the apparatus disclosed by the patent.
Schomberg, U.S. Pat. No. 4,549,280, emphasizes parity checking and modularity of the invention for use as a building block in a large scale system wherein the data flow is described as being used in a true pipeline without feedback.
The present invention as embodied in the preferred embodiment to be described herein, employs an interactive method for achieving high speed multiplication which includes feedback of partial results. Further, the apparatus, according to the present invention, does not employ parity checking but rather uses residue for checking.
As can be seen from the above discussion none of the prior art teaches the present invention.